SRAM is used to store instructions or data in computer systems. For example, consider a computer system, such as that illustrated in FIG. 1. In FIG. 1, microprocessor die 102 comprises many sub-blocks, such as register files 104 and on-chip cache 106. Microprocessor 102 may also communicate to other levels of cache, such as off-chip cache 108. Higher memory hierarchy levels, such as system memory 110, are accessed via host bus 112 and chipset 114. In addition, other off-chip functional units, such as graphics accelerator 116 and network interface controller (NIC) 118, to name just a few, may communicate with microprocessor 102 via appropriate busses or ports. SRAM is used in register files 104 and on-chip cache 106, as well as perhaps other functional units shown in FIG. 1.
As technology scales to smaller dimensions, bit-line leakage current in SRAM may be a problem if not properly addressed. Consider a prior art SRAM shown in FIG. 2, comprising N transistor cells, where for simplicity only three cells are shown explicitly. Each cell comprises 6 transistors, two for each of the two cross-coupled inverters and two access transistors with their gates connected to a wordline. During pre-charge, Prech-Eq line 202 is held LOW so that pre-charge pMOSFETs 204 and 205 are ON to charge complementary bitlines 208 and 210 HIGH, and pMOSFET 212 is ON to equalize the voltages on complementary bitlines 208 and 210. After pre-charge, when a cell is read, its corresponding wordline is held HIGH, and a sense amplifier (not shown) senses differential current developed on complementary bitlines 208 and 210 as a result of the read operation.
Suppose the data stored in the SRAM is such that node 214 in the top-most cell shown in FIG. 2 is LOW and nodes 216 in all the other cells are LOW. This presents a worse-case scenario regarding leakage current, as is now discussed. Consider a read operation performed on the top-most cell. With wordline 218 HIGH, access transistor 218 is ON to sink a current Idrive from bitline 208. The other wordlines are LOW, but because of the non-zero drain-to-source voltages in access transistors 222, each access transistor 222 leaks some current Ileak from bitline 210. As a result, the effective current for developing a differential signal senses by the sense amplifier is Idrive−(N−1)Ileak, and the effective current is thereby reduced when the leakage current increases. Consequently, as leakage current increases, there may be an increase in the likelihood of an incorrect read operation.